1. Field of the Invention
This invention relates to a method of forming a semiconductor device having self-aligned contact holes, particularly for interconnecting lines and diffused layers.
2. Description of the Prior Art
For scaling down of semiconductor devices, scaling down of lines and diffused layers in a semiconductor device, and multilevel interconnection structure are primarily needed. Scaling down of areas required for contact holes for interconnecting lines and diffused layers is essential, too. Diffused layers and the first-level lines are isolated by intermediation of insulating film such as silicon oxide film. The upper- and lower-level lines are isolated by intermediation of dielectric film such as silicon oxide film, PSG film or BPSG film. A contact hole interconnecting a diffused layer and the first-level line is formed to extend through the insulating film. A contact hole for direct connection between a diffused layer and a second or higher level line is formed with need of extending the insulating film and at least one dielectric film. These contact holes are required to have a large diameter not so as to increase electric resistance, and to minimize their areas. For this it is preferable for the margin between the contact hole and the diffused layer, {(the width of the diffused layer--diameter of the exposed surface of the diffused layer through the contact hole)/2}, to be small, at least 0. For particularly the contact hole connecting directly between a diffused layer and a second or higher level line, it is important to hold the margin to be minimized because it must be formed with need of bypassing the lower lines.
For example, in a semiconductor device containing MOS transistors, the first level lines are gate electrodes, and the diffused layers which are source and drain regions of a MOS transistor are formed to be self-aligned with a gate electrode and field oxide films. Therefore, the contact hole connecting directly between the diffused layer and the second or higher level line is formed to bypass the gate electrode. Thus a self-aligned contact hole needing minimized area has been proposed.
The structure of the self-aligned contact hole is summarized in the following by an example formed in a MOS transistor. The same respect for self-aligned and conventional contact holes directly interconnecting an upper line and a diffused layer resides in, first extending through one or more dielectric films down to a diffused layer and to bypass gate electrodes, and second, being filled with interconnect. The self-aligned contact hole is distinct from the conventional contact hole in the respect that the exposed surface of the diffused layer through the contact hole is self-aligned with the gate electrodes. Strictly speaking, the upper-level interconnect filling the self-aligned contact hole and the gate electrode must be isolated from each other, and hence the exposed surface of the diffused layer through the self-aligned contact hole has been self-aligned at a predetermined distance with respect to the gate electrodes. The gate electrodes and the self-aligned contact hole are isolated by intermediation of one of more specified insulating films each having a predetermined thickness.
Two typical method of forming self-aligned contact holes will be described under.
The first method of forming self-aligned contact holes is reported in IEICE (The Institute of Electronics, Information and Communication Engineers, JAPAN) TRANSACTIONS Vol. E74, No. 4 (April), pp. 818-826, 1991, in which in a DRAM containing information storage stacked capacitors the second-level lines are formed as bit lines, and the connection between one of them and one diffused layer of the source and drain regions is made through the self-aligned contact hole. The processing sequence of this method is as follows:
At the surface of a p-type silicon substrate are formed field oxide films and gate oxide films. Over the entire surface is formed a polysilicon film, and then thereover an about 250 nm-thick silicon oxide film is formed. These are patterned to form gate electrodes (word lines) of polysilicon film, and a silicon oxide film mask which covers the top faces of the gate electrodes. Ion implantation is performed using the silicon oxide mask, the gate electrodes and the field oxide films as masks to produce lightly-doped n-type diffused layers at the surface of the silicon substrate. Over the entire surface a silicon oxide film of 200 nm thick is formed and etched back to form silicon oxide film spacers covering the side faces of each gate electrode. Then the portions of the gate oxide film remaining uncovered with the silicon oxide film spacers and the gate electrodes are removed.
In the next step, over the whole surface an about 50 nm-thick silicon oxide film (HTO film) is formed by high temperature CVD technique, and then ion implantation is carried cut using the silicon oxide film spacers, the silicon oxide film, the gate electrodes and the field oxide films as masks to produce diffused layers (source/drain regions) each comprising a lightly-doped n-type region and a high-doped n-type region. Over the whole surface is formed an about 20 nm thick silicon nitride film, over the entire surface of which a dielectric film made from BPSG.
In the next step, a photoresist film is formed which is provided windows by means of each an opened portion is to be created on either diffused layer of the source and drain regions. Using this photoresist film as mask, the BPSG film is wet-etched with a buffered hydrofluoric acid. For this wet-etching, the silicon nitride film serves as an etching stopper. Subsequently using this photoresist film as mask, anisotropic dry etching of silicon nitride film 244 and HTO film are carried out with the same fluorocarbon-related etching gas, thereby self-aligned contact hole being opened (FIG. 1C). After removing the photoresist film, BPSG film is reflowed.
The second method of forming self-aligned contact holes is reported in Technical Digest of IEDM, pp. 473-476, 1990, in which self-aligned contact holes are used in formation of SRAM. This method is as follows:
At the surface of a p-type silicon substrate, gate oxide films, and others, are formed, and then gate electrodes with the top face covered with silicon oxide film mask (or silicon nitride film mask) and with the side faces covered with silicon oxide film spacers is formed, and then n-type diffused layers are formed. The portions of gate oxide film uncovered with the silicon oxide film spacers and the gate electrodes. Over the whole surface is formed an aluminium oxide film, further over the whole surface of which being formed a dielectric film made from BPSG, or made of a silicon oxide film produced by CVD technique using ozone and TEOS (tetraethyl orthosilicate: Si(OC.sub.2 H.sub.5).sub.4).
In the next step, a photoresist film is formed which is provided with windows corresponding to the surface portions to be exposed of the diffused layers, respectively. Using this photoresist film, the dielectric film is dry-etched anisotropically with a fluorocarbon-related gas. The aluminium oxide film then functions as etching stopper.
After removing photoresist film, using the dielectric film as mask, the aluminium oxide film is wet-etched with phosphoric acid (H.sub.3 PO.sub.4, about 60.degree. C.) to open self-aligned contact holes.
The first prior art method of forming self-aligned contact hole faces the following problems:
Previous to forming a dielectric film, a three-layered insulator consisting of silicon oxide film spacer, HTO film, and silicon nitride film, are built on each side face of a gate electrode. Hence there are two three-layered insulator between two gate electrodes. For this reason, as the first problem, a self-aligned contact hole results in having an about twice larger area than the thickness of the three-layered insulator. This method therefore may stand in the way of scaling down the semiconductor device. The HTO film can serve for preventing the surface of the diffused layer from being eroded by ammonia during formation of the silicon nitride film.
As described above, using the same photoresist film as used in the wet-etching of dielectric film, the silicon nitride film and HTO film are dry-etched with the same etching gas. Increment of area needed for the self-aligned contact hole, which is the first problem can be suppressed more or less, for example, by using a thinner one as this HTO film. The use of thinner HTO film gives rise to the second problem associated with this anisotropic dry etching. There is little difference in rate of anisotropic dry etching between silicon oxide film and silicon nitride film, this causing the portions of silicon oxide film spacers and silicon oxide film mask near to the top face edges of gate electrode to get susceptible to etching, with the result of degraded isolation between the portions of the gate electrode near their top face edges and the bit line formed by overfilling the self-aligned contact hole.
The second method of forming self-aligned contact holes described above faces problems: The first is similar to the problem presented by the first method: Previous to formation of a dielectric film, a two-layered insulator consisting of silicon oxide film spacer and an aluminium oxide film is formed on the side faces of a gate electrode, so that the self-aligned contact hole results in having about twice larger area than the thickness of the two-layered insulator, this standing in the way of scaling down the semiconductor device.
The second problem related to the second method is associated with wet etching of the aluminium oxide film which is the last stage for opening self-aligned contact holes. For example, two adjacent self-aligned contact holes can be formed by over-etch of aluminium oxide film using the wet etching technique, with the result of leaving a very thin aluminium oxide film between both self-aligned holes. Correspondingly degraded isolation between the interconnects filling two self-aligned contact holes results. In an extreme case, no aluminium oxide film may leave between the contact holes, so that the interconnects filling over the contact holes may make short circuit. This phenomenon apts to be caused by wet etching because of difficult detection of the end point of the latter. Furthermore, etching the aluminium oxide film by wet etching is carried out for avoiding the phenomenon that the aluminium oxide film is formed under the contact directly with the diffused layers where self-aligned contact holes are formed, and hence it is not preferable to perform, for example, by dry etching with a chlorine-relative, the removal of these portions of the aluminium oxide film. Dry etching with a chlorine-relative can cause the surfaces of the diffused layers to be eroded.
There is another problem common to the first and second methods of forming self-aligned contact holes. These, which are methods of forming self-aligned contact holes with the first-level line. It however is difficult to build three or more levels of interconnection structure by an widened application of these methods so that self-aligned contact holes may be formed simultaneously with respect to at least two levels of lines. In other words, in this case, a plurality of alternating etchings of dielectric films and stopper films for the etchings made as from silicon nitride or aluminium oxide is needed. For this series of etchings, the silicon oxide film spacers formed on the side faces of each line become smaller in thickness with lowering level. This reflects larger susceptibility to degradation of isolation between the interconnect filling the self-aligned contact hole and the lower-level interconnect. It is noteworthy that danger of short circuit increases between interconnect filling the self-aligned contact hole and one level lower lines. As described above the first and second methods are concluded to have low effects on three- or more level-interconnect structure.